1. Field of the Invention
The present invention relates to a sense amplifier of a semiconductor memory chip and, more particularly, to reducing the consumption of an electric current caused by a simultaneous driving of two circuits by differing the reference voltages of a discharge voltage and a power generation circuit in a part of a discharging period, when reducing the power voltage that has been raised after over-driving a sense amplifier.
2. Description of Related Art
As semiconductors become more integrated and low powered, achievement of simultaneous low driving voltages and high speed becomes desirable. Accordingly, as a driving voltage is lowered, methods have been attempted to drive a sense amplifier smoothly in a dynamic RAM (DRAM), such as through a sense amplifier over driving method.
If the data stored in a cell are selected according to the operation of a bit line sense amplifier (to be referred to as a xe2x80x98sense amplifierxe2x80x99 hereinafter), they are charge-shared and come in as bit lines having the potential of the voltage for bit line precharge (VBLP). Here, in the pull-up operation from a bit line precharge voltage VBLP to a cell power voltage DVDD, since the cell power voltage CVDD is low and, thus, the difference between the cell power voltage CVDD and the voltage for bit line precharge (VBLP) is not large, it takes a long time to raise the VBLP to the desired level of the cell power voltage CVDD. To solve this problem, the size of a transistor for pull-up in the sense amplifier may be made larger, but this approach increases the size of a semiconductor memory chip, and often there are limitations imposed on the size of a particular memory chip. Therefore, an alternative solution has been to utilize an over driving method.
Referring to FIGS. 1 and 2, the operation of a conventional over-driving method will be described hereinafter.
The cell data selected by a word line are transferred to a bit line and the bit line pair is diverged. Here, the bit lines are diverged by the width of xcex94V, and the width is determined by the ratio of the cell capacitance and the bit line capacitance. The width may range from tens of millivolts to hundreds of millivolts. The sense amplifier is driven by the diverged width and creates a value sufficient to read/write data. The next operation begins during this operation of sense amplifier.
In a first over-driving period of the sense amplifier operation, a first sense amplifier enable signal SA_EN_1 is supplied to a MOS transistor MOS1 of an external power voltage unit 110 (in case of an NMOS transistor, an xe2x80x9cHxe2x80x9d or HIGH signal; and in the case of a PMOS transistor, an xe2x80x9cLxe2x80x9d or low signal) thereby enabling the MOS transistor MOS1. In the initial period, an external power voltage VEXT, which is higher than a cell power voltage CVDD, is supplied to the sense amplifier 130 through the path A along the MOS1 and the restore line RTO and thus the potential of the restore line RTO rises sharply.
When the potential of the restore line RTO rises to a predetermined level and the over-driving period has been finished, in a second driving period, a second sense amplifier enable signal SA_EN_2 is supplied to a MOS transistor MOS2 of the cell power voltage unit 120 thereby enabling the MOS transistor MOS2. At that moment, the cell power voltage CVDD is applied to the sense amplifier 130 through the MOS transistor MOS2 and the restore line RTO and place the sense amplifier 130 into a pull-up state and maintains that state.
During the operation, a current may flow from the external power voltage unit 110, which supplies relatively high voltage to the cell power voltage unit 120 which provides a relatively low voltage, thus raising the cell power voltage CVDD. In particular, when the sense amplifier 130 is operated continuously, the influx into the cell power voltage unit 120 appears large. In the part A of FIG. 2, the restore line RTO ascends excessively, and the cell power voltage CVDD is raised as well by the effect therefrom. The use of an over-driving circuit, which operates the driving of the sense amplifier 130, which reads/writes data for high speed processes of a semiconductor memory chip, improves the performance of the memory core. However, there is a problem that the electric current consumed is excessive due to the potential gap between the two powers.
To solve this problem, a method is utilized that compares the actual cell power voltage CVDD and the reference cell power voltage VREF in the middle of or after the sense amplifier operates and conducts over-driving. If the actual cell power voltage CVDD is higher than the reference power voltage VREF, the actual cell power voltage CVDD is lowered to a desired level. However, due to the delay time in sensing between the circuit (i.e., a discharge circuit) which lowers the actual cell power voltage CVDD that has been raised and the CVDD power generation circuit that raises the reference cell power voltage VREF when the actual cell power voltage CVDD falls below the reference cell power voltage VREF, the level of the actual cell power voltage CVDD fluctuates during this operation and much electric current is consumed unnecessarily. This operation will be described more in detail, hereinafter.
FIG. 3 is a block diagram describing the structure of a semiconductor memory device in accordance with another conventional over-driving method.
As shown in FIG. 3, a semiconductor memory device of the conventional over-driving scheme includes a core unit 310 of a semiconductor memory chip using an external power voltage VEXT and the cell power voltage CVDD. A cell power voltage generation unit 320 is included for generating a cell power voltage CVDD used in the core unit 310 and a cell power voltage discharge unit 330 is included for lowering the potential of the cell power voltage CVDD that has been raised by the operation of the core unit 310.
First, in the over-driving period, the cell power voltage CVDD is raised according to over driving by the external power voltage VEXT, and in the first discharging period, a cell power voltage discharge unit 330 operates and compares the actual cell power voltage CVDD with the reference voltage VREF. As the actual cell power voltage CVDD is raised, the cell power voltage discharge unit 330 operates and pulls down the actual cell power voltage CVDD to the level of the reference voltage VREF. When the actual cell power voltage CVDD falls below the reference voltage VREF by discharging during the discharge period, the discharging operation is not immediately halted. This is due to a delay in the sensing caused by operation time of transistors within the cell power voltage discharge unit 330. Thus, the actual cell power voltage CVDD falls below the reference voltage. The actual cell power voltage CVDD is then raised due to the operation of the cell power voltage generation unit 320 via charging, but does not terminate when the actual cell power voltage CVDD reaches the reference voltage through charging due to sensing delay time caused by operation time of the transistors in the voltage generation unit 320, thereby overshooting the reference voltage. Hence, a current flows from the external power voltage VEXT to the cell power voltage CVDD, and from the cell power voltage CVDD to the source voltage VSS, respectively, owing to the repeated operations of the cell power voltage generation unit 320 and the cell power voltage discharge unit 330, causing a dampened oscillation as shown in FIG. 4. This current is consumed unnecessarily, and as the operation of a semiconductor memory chip gets faster, the amount of the current consumption increases drastically.
The present disclosure provides a current reducing device in a sense amplifier over driver scheme of a semiconductor memory chip that can reduce the amount of electric current consumed unnecessarily during the discharging operation by differing the reference voltages of a cell power voltage discharge unit and a cell power voltage generation unit during a portion of the discharging period.
According to an aspect of the presently disclosed device for use in an over driver scheme of a semiconductor memory chip, a core unit is provided including a sense amplifier of the semiconductor memory chip. Also included is a cell power voltage generation unit that is configured to use in external power voltage as a power source, wherein the cell power voltage generation unit is further configured to receive a cell power voltage, which is used as a power source for the core unit, and a first reference voltage. The cell power voltage generation unit is also configured to increase the cell power voltage when the cell power voltage is lower than the first referenced voltage. Also included is a reference voltage generation unit that is configured to output a second reference voltage different from the first reference voltage during a portion of a discharging period. A cell power voltage discharge unit is included and configured to receive and compare the second reference voltage outputted from the reference voltage generation unit and the cell power voltage. The cell power voltage discharge unit also reduces the cell power voltage when the cell power voltage is higher than the second referenced voltage.
According to another aspect of the present disclosure, a current reducing device in an over driver scheme of a semiconductor memory chip includes a core unit including a sense amplifier of the semiconductor memory chip. A cell power voltage generation unit that uses an external power voltage is a power source is configured to receive a cell power voltage, which is used as a power source for the core unit, and a first reference voltage. The cell power voltage generation unit increases the cell power voltage when the cell power voltage is lower than the first reference voltage. A comparative cell power voltage generation unit is included for use by the cell power voltage discharge unit. This unit is configured to receive a second reference voltage that is in proportion to the first reference voltage and the cell power voltage. The unit then outputs a comparative cell power voltage that is lower than a proportional cell power voltage, which is in proportion to the cell voltage by a predetermined voltage during a portion of a discharging period. Finally, a cell power voltage discharge unit is included and is configured to receive and compare the comparative cell power voltage and the second reference voltage during the discharging period and to reduce the cell power voltage when the comparative cell power voltage is higher than the second reference voltage.
According to an aspect of the presently disclosed method for reducing an electric current in a sense amplifier over driver scheme of a semiconductor memory chip, over driving is performed by an external power voltage. A second reference voltage is generated that is different from a first reference voltage inputted to a cell power voltage generation unit, which generates a cell power voltage during a portion of the discharging period. A cell power voltage that is increased by the overdriving is compared with the second reference voltage and the cell power voltage is reduced during the discharging period. The cell power voltage is raised when the cell power voltage is lower than the first reference voltage.
According to yet another aspect of the presently disclosed method for reducing electric current in a sense amplifier over driver scheme of a semiconductor chip, overdriving is performed using an external power voltage. A comparative power voltage is output that is lower than a proportional cell power voltage, which is in proportion with a cell power voltage, during a portion of a discharging period by a predetermined voltage. The comparative cell power voltage is compared with a first reference voltage and the cell power voltage is reduced, the cell power voltage having been raised by the overdriving. Finally, the cell power voltage is raised when the cell power voltage is lower than a second reference voltage that is in proportion to the first reference voltage.